Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

ABSTRACT

Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.

This invention was made with Government support under HR0011-09-C-0002awarded by Defense Advanced Research Projects Agency (DARPA). TheGovernment has certain rights in this invention.

BACKGROUND

Embodiments of the invention relate to processor arrays, and inparticular, a processor array with interconnect circuits for bondingsemiconductor dies.

A processor array contains and manages multiple processing elements.There are different types of processing elements, such asmicroprocessors, microcontrollers, digital signal processors, graphicsprocessors, reconfigurable processors, fixed function units, hardwareaccelerators, neurosynaptic neural core circuits, etc. A processor arraymay include different types of processing elements. The processingelements may be arranged in a one-dimensional array, a two-dimensionalarray, or a three-dimensional array, or a ring or torus topology. Theprocessing elements are interconnected by a routing system includingbuses and switches. Packets are communicated between processing elementsusing the routing system.

BRIEF SUMMARY

Embodiments of the invention relate to processor arrays, and inparticular, a processor array with interconnect circuits for bondingsemiconductor dies. One embodiment comprises multiple semiconductor diesand at least one interconnect circuit for exchanging signals between thedies. Each die comprises at least one processor core circuit. Eachinterconnect circuit corresponds to a die of the processor array. Eachinterconnect circuit comprises one or more attachment pads forinterconnecting a corresponding die with another die, and at least onemultiplexor structure configured for exchanging bus signals in areversed order.

Another embodiment of the invention comprises exchanging signals betweenmultiple semiconductor dies via at least one interconnect circuit. Eachdie comprises at least one processor core circuit. Each interconnectcircuit corresponds to a die of the processor array. Each interconnectcircuit comprises one or more attachment pads for interconnecting acorresponding die with another die, and at least one multiplexorstructure configured for exchanging bus signals in a reversed order.

These and other features, aspects and advantages of the presentinvention will become understood with reference to the followingdescription, appended claims and accompanying figures.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A illustrates a one-dimensional (1-D) array of processor corecircuits, in accordance with an embodiment of the invention;

FIG. 1B illustrates a two-dimensional (2-D) array of processor corecircuits, in accordance with an embodiment of the invention;

FIG. 1C illustrates a three-dimensional (3-D) array of processor corecircuits, in accordance with an embodiment of the invention;

FIG. 2 illustrates an example configuration of a switch in FIG. 1,wherein the switch is a 3-D switch, in accordance with an embodiment ofthe invention;

FIG. 3 illustrates another example configuration of a switch in FIG. 1,wherein the 3-D switch is implemented in a two-dimensional (2-D) plane,in accordance with an embodiment of the invention;

FIG. 4 illustrates bonding tiers face-to-back, in accordance with anembodiment of the invention;

FIG. 5 illustrates bonding tiers face-to-face, in accordance with anembodiment of the invention;

FIG. 6A illustrates the physical orientation of two tiers of a 1-D arraythat are bonded face-to-back, in accordance with an embodiment of theinvention;

FIG. 6B illustrates the physical orientation of two tiers of a 1-D arraythat are bonded face-to-face by flipping a die about the Y-axis, inaccordance with an embodiment of the invention;

FIG. 7A illustrates the physical orientation of two tiers of a 2-D arraythat are bonded face-to-back, in accordance with an embodiment of theinvention;

FIG. 7B illustrates the physical orientation of two tiers of a 2-D arraythat are bonded face-to-face by flipping a die about the Y-axis, inaccordance with an embodiment of the invention;

FIG. 8A illustrates the physical orientation of two tiers that arebonded face-to-back, in accordance with an embodiment of the invention;

FIG. 8B illustrates the physical orientation of two tiers that arebonded face-to-face by flipping a die about the Y-axis, in accordancewith an embodiment of the invention;

FIG. 8C illustrates the physical orientation of two tiers that arebonded face-to-face by flipping a die about the X-axis, in accordancewith an embodiment of the invention;

FIG. 9 illustrates an example mirror-reversing routing circuit forreversing the logical direction of router channels, in accordance withan embodiment of the invention;

FIG. 10 illustrates a cross-sectional view of an examplemirror-reversing interconnect circuit of a tier for bonding with adifferent tier, in accordance with an embodiment of the invention;

FIG. 11 illustrates core circuits having an odd number of pads, whereinthe pads have horizontally symmetrical physical locations, in accordancewith an embodiment of the invention;

FIG. 12 illustrates core circuits having an even number of pads, whereinthe pads have horizontally symmetrical physical locations, in accordancewith an embodiment of the invention;

FIG. 13 illustrates core circuits having an odd number of pads, whereinthe pads have vertically symmetrical physical locations, in accordancewith an embodiment of the invention;

FIG. 14 illustrates core circuits having an even number of pads, whereinthe pads have vertically symmetrical physical locations, in accordancewith an embodiment of the invention;

FIG. 15 illustrates straight-through buses, in accordance with anembodiment of the invention;

FIG. 16 illustrates straight-through buses and reversed buses, inaccordance with an embodiment of the invention;

FIG. 17 illustrates core circuits having pads with verticallysymmetrical physical locations, wherein each pad is disposed along acenter axis of a core circuit, in accordance with an embodiment of theinvention;

FIG. 18 illustrates core circuits having pads with horizontallysymmetrical physical locations, wherein each pad is disposed along acenter axis of a core circuit, in accordance with an embodiment of theinvention; and

FIG. 19 is a high-level block diagram showing an information processingcircuit useful for implementing one embodiment of the invention.

DETAILED DESCRIPTION

Embodiments of the invention relate to processor arrays, and inparticular, a processor array with interconnect circuits for bondingsemiconductor dies. One embodiment comprises multiple semiconductor diesand at least one interconnect circuit for exchanging signals between thedies. Each die comprises at least one processor core circuit. Eachinterconnect circuit corresponds to a die of the processor array. Eachinterconnect circuit comprises one or more attachment pads forinterconnecting a corresponding die with another die, and at least onemultiplexor structure configured for exchanging bus signals in areversed order.

Another embodiment of the invention comprises exchanging signals betweenmultiple semiconductor dies via at least one interconnect circuit. Eachdie comprises at least one processor core circuit. Each interconnectcircuit corresponds to a die of the processor array. Each interconnectcircuit comprises one or more attachment pads for interconnecting acorresponding die with another die, and at least one multiplexorstructure configured for exchanging bus signals in a reversed order.

For each interconnect circuit corresponding to a die, one or moreattachment pads are positioned substantially symmetrical on the die,wherein the attachment pads interconnect the die with another die thatis either identical to or different from the die.

For each interconnect circuit, at least one attachment pad of theinterconnect circuit connects a core circuit of a corresponding die withanother core circuit of another die.

For each interconnect circuit, at least one attachment pad of theinterconnect circuit connects a switching circuit of a corresponding diewith another switching circuit of another die.

In one embodiment, for each core circuit, the attachment padsinterconnecting the core circuit with another core circuit arepositioned vertically relative to one another on the core circuit. Inanother embodiment, for each core circuit, the attachment padsinterconnecting the core circuit with another core circuit arepositioned horizontally relative to one another on the core circuit. Inyet another embodiment, for each core circuit, the attachment padsinterconnecting the core circuit with another core circuit arepositioned along a center axis of the core circuit.

Each multiplexor structure is configured for exchanging signals in areversed order based on one or more configuration bits.

For a first die and a second die having different physical orientations,a logical orientation of the first die is reversed to match a logicalorientation of the second die by receiving incoming signals in areversed order and sending outgoing signals in a reversed order.

In one embodiment, a top side of the first die is physically bonded witha top side of the second die. In another embodiment, a bottom side ofthe first die is physically bonded with a bottom side of the second die.

FIG. 1A illustrates a one-dimensional (1-D) array 130 of processor corecircuits 10, in accordance with an embodiment of the invention. Aprocessor core circuit 10 is a processing element for executinginstructions and processing data (e.g., generating data, consuming data,transforming data, evaluating data, storing data, retrieving data,etc.). Multiple core circuits 10 may be arranged into an N-dimensionalarray (e.g., a 1-D array or a multi-dimensional array), wherein N is apositive integer. The N-dimensional array is implemented inthree-dimensional very-large-scale integration (3D VLSI). For example,as shown in FIG. 1A, multiple core circuits 10 may be organized into aone-dimensional (1-D) array 130 implemented in 3D VLSI.

The array 130 includes multiple reversible tiers 540, such as Tier 0,Tier 1, and Tier 2. Each tier 540 of the array 130 includes a corecircuit 10. The array 130 further comprises a routing system 131 forrouting packets between the core circuits 10 in different tiers 540. Inone embodiment, the routing system 131 includes multiple 1-D switches(i.e., routers) 132 and multiple data paths (i.e., buses) 30. Eachswitch 132 corresponds to at least one core circuit 10 of the array 130.Each switch 132 is interconnected with a corresponding core circuit 10via at least one data path 30. Each switch 132 is further interconnectedwith at least one adjacent neighboring switch 132 via at least one datapath 30.

In one embodiment, each core circuit 10 of the array 130 utilizes acorresponding switch 132 to pass along packets including information tocore circuits 10 in different tiers 540 in multiple directions, such asa first Z direction with increasing Z coordinates (“Z+ direction”), anda second Z direction with decreasing Z coordinates (“Z− direction”). Zrouting (i.e., routing packets in the Z+ direction or the Z− direction)interconnects switches 132 in different tiers 540.

FIG. 1B illustrates a two-dimensional (2-D) array 140 of processor corecircuits 10, in accordance with an embodiment of the invention. In oneembodiment, multiple core circuits 10 may be organized into atwo-dimensional (2-D) array 140 implemented in 3D VLSI, as shown in FIG.1B.

The array 140 includes multiple reversible tiers 540, such as Tier 0,Tier 1, and Tier 2. Each tier 540 of the array 140 includes at least onecore circuit 10. The array 140 further comprises a routing system 141for routing packets between the core circuits 10. In one embodiment, therouting system 141 includes multiple 2-D switches (i.e., routers) 142and multiple data paths (i.e., buses) 30. Each switch 142 corresponds toat least one core circuit 10 of the array 140. Each switch 142 isinterconnected with a corresponding core circuit 10 via at least onedata path 30. Each switch 142 is further interconnected with at leastone adjacent neighboring switch 142 via at least one data path 30.

In one embodiment, each core circuit 10 of the array 140 utilizes acorresponding switch 142 to pass along packets including information tocore circuits 10 in multiple directions, such as a first X directionwith increasing X coordinates (“X+ direction”), a second X directionwith decreasing X coordinates (“X− direction”), a first Z direction withincreasing Z coordinates (“Z+ direction”), and a second Z direction withdecreasing Z coordinates (“Z− direction”). Z routing (i.e., routingpackets in the Z+ direction or the Z− direction) interconnects switches142 in different tiers 540. X routing (i.e., routing packets in the X+direction or the X− direction) interconnects switches 142 within thesame tier 540.

FIG. 1C illustrates a three-dimensional (3-D) array 100 of processorcore circuits 10, in accordance with an embodiment of the invention. Inone embodiment, multiple core circuits 10 may be organized into a 3-Darray 100 implemented in 3D VLSI, as shown in FIG. 1C.

The 3-D array 100 includes multiple reversible tiers 540, such as Tier0, Tier 1, and Tier 2. Each tier 540 includes at least one core circuit10. The 3-D array 100 further comprises a routing system 15 for routingpackets between the core circuits 10. The routing system 15 includesmultiple switches (i.e., routers) 20 and multiple data paths (i.e.,buses) 30. Each switch 20 corresponds to at least one core circuit 10 ofthe 3-D array 100. Each switch 20 is interconnected with a correspondingcore circuit 10 via at least one data path 30. Each switch 20 is furtherinterconnected with at least one adjacent neighboring switch 20 via atleast one data path 30.

In one embodiment, each core circuit 10 utilizes a corresponding switch20 to pass along packets including information to other core circuits 10in multiple directions, such as a first X direction with increasing Xcoordinates (“X+ direction”), a second X direction with decreasing Xcoordinates (“X− direction”), a first Y direction with increasing Ycoordinates (“Y+ direction”), a second Y direction with decreasing Ycoordinates (“Y− direction”), a first Z direction with increasing Zcoordinates (“Z+ direction”), and a second Z direction with decreasing Zcoordinates (“Z− direction”). Z routing (i.e., routing packets in the Z+direction or the Z− direction) interconnects switches 20 in differenttiers 540. X-Y routing (i.e., routing packets in the X+ direction, theX− direction, the Y+ direction, or the Y− direction) interconnectsswitches 20 within the same tier 540.

FIG. 2 illustrates an example configuration of a switch 20 in FIG. 1,wherein the switch 20 is a 3-D switch, in accordance with an embodimentof the invention. In one embodiment, the routing system 15 is amulti-dimensional switch network, wherein each switch 20 is a 3-Dswitch.

In one embodiment, each switch 20 exchanges packets with neighboringcomponents (i.e., adjacent switches 20, a corresponding core circuit 10)via multiple sets of router channels, wherein each set of routerchannels has an incoming router channel 30F and a reciprocal routerchannel 30B. Specifically, a first set 25L of router channels (“Localrouter channels”) interconnects the switch 20 with a corresponding corecircuit 10. The switch 20 receives packets from the corresponding corecircuit 10 via an incoming router channel 30F of the set 25L and sendspackets to the corresponding core circuit 10 via an outgoing routerchannel 30B of the set 25L.

A second set 25X1 of router channels (“X+ router channels”)interconnects the switch 20 with a neighboring switch 20 in the X+direction. The switch 20 receives packets from the neighboring switch 20in the X+ direction via an incoming router channel 30F of the set 25X1and sends packets to the neighboring switch 20 in the X+ direction viaan outgoing router channel 30B of the set 25X1.

A third set 25X2 of router channels (“X− router channels”) interconnectsthe switch 20 with a neighboring switch 20 in the X− direction. Theswitch 20 receives packets from the neighboring switch 20 in the X−direction via an incoming router channel 30F of the set 25X2 and sendspackets to the neighboring switch 20 in the X− direction via an outgoingrouter channel 30B of the set 25X2.

A fourth set 25Y1 of router channels (“Y+ router channels”)interconnects the switch 20 with a neighboring switch 20 in the Y+direction. The switch 20 receives packets from the neighboring switch 20in the Y+ direction via an incoming router channel 30F of the set 25Y1and sends packets to the neighboring switch 20 in the Y+ direction viaan outgoing router channel 30B of the set 25Y1.

A fifth set 25Y2 of router channels (“Y− router channels”) interconnectsthe switch 20 with a neighboring switch 20 in the Y− direction. Theswitch 20 receives packets from the neighboring switch 20 in the Y−direction via an incoming router channel 30F of the set 25Y2 and sendspackets to the neighboring switch 20 in the Y− direction via an outgoingrouter channel 30B of the set 25Y2.

A sixth set 25Z1 of router channels (“Z+ router channels”) interconnectsthe switch 20 with a neighboring switch 20 in the Z+ direction. Theswitch 20 receives packets from the neighboring switch 20 in the Z+direction via an incoming router channel 30F of the set 25Z1 and sendspackets to the neighboring switch 20 in the Z+ direction via an outgoingrouter channel 30B of the set 25Z1.

A seventh set 25Z2 of router channels (“Z− router channels”)interconnects the switch 20 with a neighboring switch 20 in the Z−direction. The switch 20 receives packets from the neighboring switch 20in the Z− direction via an incoming router channel 30F of the set 25Z2and sends packets to the neighboring switch 20 in the Z− direction viaan outgoing router channel 30B of the set 25Z2.

In another embodiment, each switch 20 of the routing system 15 is aplanar switch 20 implemented in a 2-D plane.

FIG. 3 illustrates another example configuration of a switch 20 in FIG.1, wherein the 3-D switch 20 is implemented in a 2-D plane, inaccordance with an embodiment of the invention. Each switch 20 exchangespackets with neighboring components (i.e., adjacent switches 20, acorresponding core circuit 10) via multiple sets of router channels,such as a first set 25L of router channels (“Local router channels”)interconnecting the switch 20 with a corresponding core circuit 10, asecond set 25X1 of router channels (“X+ router channels”)interconnecting the switch 20 with a neighboring switch 20 in the X+direction, a third set 25X2 of router channels (“X− router channels”)interconnecting the switch 20 with a neighboring switch 20 in the X−direction, a fourth set 25Y1 of router channels (“Y+ router channels”)interconnecting the switch 20 with a neighboring switch 20 in the Y+direction, a fifth set 25Y2 of router channels (“Y− router channels”)interconnecting the switch 20 with a neighboring switch 20 in the Y−direction, a sixth set 25Z1 of router channels (“Z+ router channels”)interconnecting the switch 20 with a neighboring switch 20 in the Z+direction, and a seventh set 25Z2 of router channels (“Z− routerchannels”) interconnecting the switch 20 with a neighboring switch 20 inthe Z− direction. Each set of router channels includes at least oneincoming router channel 30F and at least one outgoing router channel30B.

FIG. 4 illustrates bonding tiers 540 face-to-back, in accordance with anembodiment of the invention. In one embodiment, an array of processorcore circuits (e.g., a 1-D array 130, a 2-D array 140, or a 3-D array100) is instantiated as an array of cores on a die, wherein each die 545represents a tier 540. For example, as shown in FIG. 4, each Tier 0, 1of the 3-D array 100 is represented by a die 545.

In another embodiment, an array of processor core circuits (e.g., a 1-Darray 130, a 2-D array 140, or a 3-D array 100) is instantiated as anarray of dies on a semiconductor wafer (or substrate) 545, wherein eachwafer (or fraction of wafer, or fraction of substrate) 545 represents atier 540. For example, each Tier 0, 1 of the 3-D array 100 may berepresented by a wafer (or substrate) 545.

Each die 545 has a top side 545A and a back side 545B. Each core circuit10 integrated on each die 545 has a corresponding physical label (i.e.,index) identifying its physical location on the die 545. For example, asshown in FIG. 4, the core circuits 10 of each Tier 0, 1 have physicallabels that identify said core circuits 10 as core circuits C00, C01,C02, C10, C11, C12, C20, C21, and C22.

The dies 545 representing the tiers 540 of an array of processor corecircuits may be bonded face-to-back, face-to-face or back-to-back. Afirst die 545 is bonded face-to-back with a second die 545 when the topside 545A of the first die 545 is bonded with the back side 545B of thesecond die 545, as shown in FIG. 4. When the tiers 540 are bondedface-to-back, the physical orientation of each tier 540 is the same. Asshown in FIG. 4, each core circuit 10 of Tier 1 is vertically alignedwith a core circuit 10 of Tier 2 having the same physical label as saidcore circuit 10. For example, core circuit C00 of Tier 1 is aligned withcore circuit C00 of Tier 0.

As the physical orientation of each tier 540 of an array of processorcore circuits is the same when the tiers 540 are bonded face-to-back,the same type of die 545 may be used to represent each tier 540.

FIG. 5 illustrates bonding tiers 540 face-to-face, in accordance with anembodiment of the invention. A first die 545 is bonded face-to-face witha second die 545 when the top side 545A of the first die 545 is bondedwith the top side 545A of the second die 545, as shown in FIG. 5. A die545 may be flipped about the X axis or about the Y axis to bond the topside 545A of the die 545 with the top side 545A of another die 545. Asshown in FIG. 5, the die 545 representing Tier 1 is flipped about the Xaxis to bond Tiers 0 and 1 face-to-face.

When the tiers 540 of an array of processor core circuits are bondedface-to-face, the tiers 540 have different physical orientations. Asshown in FIG. 5, at least one core circuit 10 of Tier 1 is notvertically aligned with a core circuit 10 of Tier 0 having the samephysical label as said at least one core circuit 10. For example, corecircuit C00 of Tier 1 is vertically aligned with core circuit C02 ofTier 0, not core circuit C00 of Tier 0.

A first die 545 is bonded back-to-back with a second die 545 when theback side 545B of the first die 545 is bonded with the back side 545B ofthe second die 545. A die 545 may be flipped about the X axis or aboutthe Y axis to bond the back side 545B of the die 545 with the back side545B of another die 545. Like face-to-face bonding, the tiers 540 of anarray of processor core circuits have different physical orientationswhen the tiers 540 are bonded back-to-back.

As described in detail later herein, the present invention allows thesame type of die 545 to be used when bonding the tiers 540 of an arrayof processor core circuits face-to-face or back-to-back. This removesthe need to use different types of dies 545 when bonding the tiers 540of an array of processor core circuits face-to-face or back-to-back.

The present invention allows for the same type of die 545 to be used foreach tier 540 of an array of processor core circuits. In one embodiment,a software, firmware, or compiler utilizing an array of processor corecircuits maps each core circuit 10 to a logical label, wherein eachlogical label represents a logical position of the core circuit 10 inthe array. Therefore, the physical orientation of each tier 540 istransparent to the software. The dies 545 may be bonded face-to-facewithout using different types of dies 545.

FIG. 6A illustrates the physical orientation of two tiers 540 of a 1-Darray 130 that are bonded face-to-back, in accordance with an embodimentof the invention. The physical orientation of each tier 540 of the 1-Darray 130 is the same when the dies 545 representing the tiers 540 arebonded face-to-back. The interconnections between the tiers 540 arealigned. For example, each set of Z− router channels 25Z2 in Tier 1 isaligned with a set of Z+ router channels 25Z1 in Tier 0. Therefore, nomirror reversing is needed when the tiers 540 of the 1-D array 130 arebonded face-to-back.

FIG. 6B illustrates the physical orientation of two tiers 540 of a 1-Darray 130 that are bonded face-to-face by flipping a die 545 about theX-axis or Y-axis, in accordance with an embodiment of the invention. Thephysical orientation of Tier 0 is different from the physicalorientation of Tier 1 when the dies 545 corresponding to Tiers 0 and 1are bonded face-to-face. FIG. 6B illustrates the physical orientation ofTiers 0 and 1 when the die 545 representing Tier 1 is flipped about theY-axis. The interconnections between the tiers 540 are reversed. Forexample, since the physical location of each set of Z+ router channels25Z1 and Z− router channels 25Z2 in Tier 1 is reversed, each set of Z+router channels 25Z1 in Tier 0 is aligned with a set of Z+ routerchannels 25Z1 in Tier 1. This is different from FIG. 6A wherein each setof Z+ router channels 25Z1 in Tier 0 is aligned with a set of Z− routerchannels 25Z2 in Tier 1.

As described in detail later herein, to align each set of Z+ routerchannels 25Z1 in Tier 0 with a set of Z− router channels 25Z2 in Tier 1,the logical direction of each set of Z+ router channels 25Z1 and Z−router channels 25Z2 in Tier 1 is reversed. Therefore, reversing thelogical direction of the Z+ router channels 25Z1 and the Z− routerchannels 25Z2 in Tier 1 adjusts the logical orientation of Tier 1 suchthat the logical orientation of Tier 1 matches the physical and logicalorientation of Tier 0.

FIG. 7A illustrates the physical orientation of two tiers 540 of a 2-Darray 140 that are bonded face-to-back, in accordance with an embodimentof the invention. The physical orientation of each tier 540 of the 2-Darray 140 is the same when the dies 545 representing the tiers 540 arebonded face-to-back. The interconnections between the tiers 540 arealigned. For example, each set of Z− router channels 25Z2 in Tier 1 isaligned with a set of Z+ router channels 25Z1 in Tier 0. Therefore, nomirror reversing is needed when the tiers 540 of the 2-D array 140 arebonded face-to-back.

FIG. 7B illustrates the physical orientation of two tiers 540 of a 2-Darray 140 that are bonded face-to-face by flipping a die 545 about theY-axis, in accordance with an embodiment of the invention. As statedabove, the physical orientation of Tier 0 is different from the physicalorientation of Tier 1 when the dies 545 corresponding to Tiers 0 and 1are bonded face-to-face. FIG. 7B illustrates the physical orientation ofTiers 0 and 1 when the die 545 representing Tier 1 is flipped about theY-axis. The interconnections between the tiers 540 are reversed. Forexample, since the physical location of each set of Z+ router channels25Z1 and Z− router channels 25Z2 in Tier 1 is reversed, each set of Z+router channels 25Z1 in Tier 0 is aligned with a set of Z+ routerchannels 25Z1 in Tier 1. This is different from FIG. 7A wherein each setof Z+ router channels 25Z1 in Tier 0 is aligned with a set of Z− routerchannels 25Z2 in Tier 1.

As described in detail later herein, to align each set of Z+ routerchannels 25Z1 in Tier 0 with a set of Z− router channels 25Z2 in Tier 1,the logical direction of each set of Z+ router channels 25Z1 and Z−router channels 25Z2 in Tier 1 is reversed.

Also shown in FIG. 7B, the physical location of each set of X+ routerchannels 25X1 and X− router channels 25X2 in Tier 1 is reversed. As aresult, X routing between the core circuits 10 in Tier 1 is reversed(i.e., opposite of X routing between the core circuits 10 in Tier 0). Asdescribed in detail later herein, the logical direction of each set ofX+ router channels 25X1 and X− router channels 25X2 in Tier 1 isreversed so that X routing between the core circuits 10 in Tier 1matches X routing between the core circuits 10 in Tier 0.

Therefore, reversing the logical direction of the Z+ router channels25Z1, the Z− router channels 25Z2, the X+ router channels 25X1, and theX− router channels 25X2 in Tier 1 adjusts the logical orientation ofTier 1 such that the logical orientation of Tier 1 matches the physicaland logical orientation of Tier 0.

FIG. 8A illustrates the physical orientation of two tiers 540 of a 3-Darray 100 that are bonded face-to-back, in accordance with an embodimentof the invention. The physical orientation of each tier 540 of the 3-Darray 100 is the same when the dies 545 representing the tiers 540 arebonded face-to-back. The interconnections between the tiers 540 arealigned. For example, each set of Z− router channels 25Z2 in Tier 1 isaligned with a set of Z+ router channels 25Z1 in Tier 0. Therefore, nomirror reversing is needed when the tiers 540 of the 3-D array 100 arebonded face-to-back.

FIG. 8B illustrates the physical orientation of two tiers 540 of a 3-Darray 100 that are bonded face-to-face by flipping a die 545 about theY-axis, in accordance with an embodiment of the invention. As statedabove, the physical orientation of Tier 0 is different from the physicalorientation of Tier 1 when the dies 545 corresponding to Tiers 0 and 1are bonded face-to-face. FIG. 8B illustrates the physical orientation ofTiers 0 and 1 when the die 545 representing Tier 1 is flipped about theY-axis. The interconnections between the tiers 540 are reversed. Forexample, since the physical location of each set of Z+ router channels25Z1 and Z− router channels 25Z2 in Tier 1 is reversed, each set of Z+router channels 25Z1 in Tier 0 is aligned with a set of Z+ routerchannels 25Z1 in Tier 1. This is different from FIG. 8A wherein each setof Z+ router channels 25Z1 in Tier 0 is aligned with a set of Z− routerchannels 25Z2 in Tier 1.

As described in detail later herein, to align each set of Z+ routerchannels 25Z1 in Tier 0 with a set of Z− router channels 25Z2 in Tier 1,the logical direction of each set of Z+ router channels 25Z1 and Z−router channels 25Z2 in Tier 1 is reversed.

Also shown in FIG. 8B, the physical location of each set of X+ routerchannels 25X1 and X− router channels 25X2 in Tier 1 is reversed. As aresult, X routing between the core circuits 10 in Tier 1 is reversed(i.e., opposite of X routing between the core circuits 10 in Tier 0). Asdescribed in detail later herein, the logical direction of each set ofX+ router channels 25X1 and X− router channels 25X2 in Tier 1 isreversed so that X routing between the core circuits 10 in Tier 1matches X routing between the core circuits 10 in Tier 0.

Therefore, reversing the logical direction of the Z+ router channels25Z1, the Z− router channels 25Z2, the X+ router channels 25X1, and theX− router channels 25X2 in Tier 1 adjusts the logical orientation ofTier 1 such that the logical orientation of Tier 1 matches the physicaland logical orientation of Tier 0.

FIG. 8C illustrates the physical orientation of two tiers 540 of a 3-Darray 100 that are bonded face-to-face by flipping a die 545 about theX-axis, in accordance with an embodiment of the invention. The physicalorientation of Tier 0 is different from the physical orientation of Tier1 when the dies 545 corresponding to Tiers 0 and 1 are bondedface-to-face. FIG. 8C illustrates the physical orientation of Tiers 0and 1 when the die 545 representing Tier 1 is flipped about the X-axis.The interconnections between the tiers 540 are reversed. For example,since the physical location of each set of Z+ router channels 25Z1 andZ− router channels 25Z2 in Tier 1 is reversed, each set of Z+ routerchannels 25Z1 in Tier 0 is aligned with a set of Z+ router channels 25Z1in Tier 1. This is different from FIG. 8A wherein each set of Z+ routerchannels 25Z1 in Tier 0 is aligned with a set of Z− router channels 25Z2in Tier 1.

As described in detail later herein, to align each set of Z+ routerchannels 25Z1 in Tier 0 with a set of Z− router channels 25Z2 in Tier 1,the logical direction of each set of Z+ router channels 25Z1 and Z−router channels 25Z2 in Tier 1 is reversed.

Also shown in FIG. 8C, the physical location of each set of Y+ routerchannels 25Y1 and Y− router channels 25Y2 in Tier 1 is reversed. As aresult, Y routing between the core circuits 10 in Tier 1 is reversed(i.e., opposite of Y routing between the core circuits 10 in Tier 0). Asdescribed in detail later herein, the logical direction of each set ofY+ router channels 25Y1 and Y− router channels 25Y2 in Tier 1 isreversed so that Y routing between the core circuits 10 in Tier 1matches Y routing between the core circuits 10 in Tier 0.

Therefore, reversing the logical direction of the Z+ router channels25Z1, the Z− router channels 25Z2, the Y+ router channels 25Y1, and theY− router channels 25Y2 in Tier 1 adjusts the logical orientation ofTier 1 such that the logical orientation of Tier 1 matches the physicaland logical orientation of Tier 0.

FIG. 9 illustrates an example mirror-reversing routing circuit 150 forreversing the logical direction of router channels, in accordance withan embodiment of the invention. In one embodiment, the physicalorientation of each tier 540 of an array of processor core circuits istransparent to any computer program product (i.e., software, compiler)utilizing the array. The physical location of each core circuit 10 in anarray of processor core circuits is mapped to a logical labelidentifying a logical location, thereby allowing the computer programproduct to utilize logical locations, instead of physical locations,during computation. For example, when Tiers 0 and 1 are bondedface-to-face as shown in FIG. 5, the core circuits 10 in Tier 1 withphysical labels C00, C01, C02, C10, C11, C12, C20, C21, and C22 arelogically mapped as core circuits 10 with logical labels C02, C01, C00,C12, C11, C10, C22, C21, and C20, respectively.

In one embodiment, each switch 20 includes at least one routing circuit150 for reversing the logical direction of some router channels. Eachcircuit 150 maintains dimension ordered routing (i.e., there is noswapping between X, Y and Z routing).

In one embodiment, each circuit 150 is configured for absoluteaddressing. Each circuit 150 of each switch 20 includes a programmableposition register for maintaining a corresponding self address (e.g. theaddress of the switch 20). For example, during normal operation (i.e.,not in mirror-reversing mode), each circuit 150 determines whether adestination address (i.e., route word) for a packet is greater than thecorresponding self address of the circuit 150. If the destinationaddress is greater than the corresponding self address, the circuit 150sends the packet in the X+ direction 25X1. Otherwise, it sends thepacket in the X− direction 25X2. If the circuit 150 is set tomirror-reverse mode using a mirror-reversing select bit Sel, the circuit150 logically reverses the direction that the packet is sent. In thiscase, the circuit 150 sends the packet in the X+ direction 25X1 if thedestination address is less than the corresponding self address.Otherwise, it sends the packet in the X− direction 25X2.

For example, in one embodiment, a circuit 150 for a set of Local routerchannels 25L of a switch 20 comprises a first comparison unit 28, asecond comparison unit 29, a reverse selector unit 26, and a routingunit 27. For each packet received from a corresponding core circuit 10via an incoming router channel 30F of the set of Local router channels25L, the destination address of the packet is provided to the comparisonunits 28 and 29. The first comparison unit 28 determines whether thedestination address is greater than the corresponding self address ofthe circuit 150. The second comparison unit 29 determines whether thedestination address is less than the corresponding self address of thecircuit 150. The multiplexor 26 selects between the greater than andless than operations, based on the mirror-reversing select bit Sel.

The reverser selector unit 26 receives the select bit Sel from anexternal mirror-reversing module 175. The mirror-reversing module 175configures the select bit Sel based on whether the tiers 540 of thearray of processor core circuits are bonded face-to-back, face-to-face,or back-to-back. For example, the mirror-reversing module 175 sets theselect bit Sel (e.g., to “1”) when the tiers 540 of the array ofprocessor core circuits are bonded face-to-face or back-to-back. Thereverse selector unit 26 is configured to enable mirror reversing basedon the select bit Sel and the comparison units 28 and 29. Specifically,if the destination address is greater than or less than thecorresponding self address of the circuit 150 and the select bit Sel isset (e.g., to “1”), the reverse selector unit 26 enablesmirror-reversing. If mirror reversing is enabled, the routing unit 27routes the packet in a direction opposite of normal operation (i.e., notmirror-reversing mode). For example, if the destination address is inthe X+ direction, the circuit 150 routes the packet in the X− directioninstead. If the destination address is the same as the correspondingself address of the circuit 150 or the select bit Sel is not set (e.g.,is “0”), the reverse selector unit 26 disables mirror-reversing. Ifmirror reversing is disabled, the routing unit 27 routes the packet inthe direction corresponding to the destination address. For example, ifthe destination address is in the X+ direction, the circuit 150 routesthe packet in the X+ direction.

In one embodiment, when the select bit Sel is set, each switch 20 isconfigured to: (1) route packets from the Local router channels 25L withdestination addresses in the X+ or the X− direction to the X− or the X+direction, respectively; (2) route packets from the X+ or X− routerchannels 25X1, 25X2 with destination addresses in the Y+ or the Y−direction to the Y− or the Y+ direction, respectively; and (3) routepackets from the Y+ or Y− router channels 25Y1, 25Y2 with destinationaddresses in the Z+ or the Z− direction to the Z− or the Z+ direction,respectively.

In another embodiment, the circuit 150 is configured for relativeaddressing. The circuit 150 determines whether the destination addressfor a packet is a positive (+) address (i.e., an address in the Z+, X+or Y+ direction) or a negative (−) address (i.e., an address in the Z−,X− or Y− direction). If the destination address for a packet is apositive address and the select bit Sel is set, the circuit 150 reversesthe destination address to a negative address. If the destinationaddress for a packet is a negative address and the select bit Sel isset, the circuit 150 reverses the destination address to a positiveaddress.

Each tier 540 includes top, bottom, and through-substrate interconnectcircuits 200 (FIG. 10) for bonding with a different tier 540.

FIG. 10 illustrates a cross-sectional view of an examplemirror-reversing interconnect circuit 200 of a tier 540 for bonding witha different tier 540, in accordance with an embodiment of the invention.In one embodiment, each die 545 representing a tier 540 has a metallictop contact 20A and a metallic back contact 20B. Each contact 20A, 20Bof each die 545 includes at least one interconnect pad 21 for each corecircuit 10 integrated on said die 545. Each pad 21 of each contact 20A,20B is used for bonding said contact 20A, 20B with a contact 20A or 20Bof another die 545.

In one embodiment, each pad 21 disposed on the top contact 20A isvertically aligned with a pad 21 disposed on the back contact 20B. Forexample, a first pad P0 of the top contact 20A is vertically alignedwith a first pad P0 of the back contact 20B.

In one embodiment, each die 545 further comprises a metal stack 22, anactive device 23, and a substrate 24. In one embodiment, the activedevices 23 are transistors. The metal stack 22 and the active devices 23comprise all of the computation, communication, and memory circuits onthe die 545, such as switches, routers, processing cores, memory, etc.

In one embodiment, the pads 21 are physically positioned such that thepads 21 are symmetric across mirroring dimensions.

FIG. 11 illustrates core circuits 10 having an odd number of pads 21,wherein the pads 21 have horizontally symmetrical physical locations, inaccordance with an embodiment of the invention. In one embodiment, eachcore circuit 10 has at least one row 21R of pads 21. Each row 21Rcomprises N pads 21, wherein N is an odd or even numbered integer. Forexample, as shown in FIG. 11, each core circuit 10 has 3 contact pads21, such as a first pad P0, a second pad P1, and a third pad P2.

In one embodiment, each core circuit 10 has a first side 10A and asecond side 10B that is opposite of the first side 10A. Let i denote theindex of a pad 21 within each row 21R. As shown in FIG. 11, the pads 21on each core circuit 10 have horizontally symmetrical physicallocations. Specifically, each i^(th) pad within a row 21R of a corecircuit 10 is arranged such that the distance from the first side 10A ofthe core circuit 10 to said i^(th) pad is equal to the distance from thesecond end 10B of the core circuit 10 to the (N−i−1)^(th) pad of the row21R, wherein in i=0, . . . , N−1. For example, as shown in FIG. 11, thedistance x₁ between pad P0 of core circuit Core1 and the first side 10Aof core circuit Core1 is equal to the distance x₁ between pad P2 of corecircuit Core1 and the second side 10B of core circuit Core1. Also shownin FIG. 11, the distance x₂ between pad P1 of core circuit Core1 and thefirst side 10A of core circuit Core1 is equal to the distance x₂ betweenpad P1 of core circuit Core1 and the second side 10B of core circuitCore1.

In one embodiment, each die 545 has a peripheral area 545P with a widthx₀. The distance x₀ from an edge of the die 545 to an edge of the corecircuit Core0 is equal to the distance x₀ from an opposite edge of thedie 545 to an edge of the core circuit Core1.

Since the pads 21 on each core circuit 10 have horizontally symmetricalphysical locations, the pads 21 on a first die 545 vertically align withthe pads 21 on a second die 545 when the first and second dies 545 arebonded face-to-back, face-to-face, or back-to-back.

FIG. 12 illustrates core circuits 10 having an even-number of pads 21,wherein the pads 21 have horizontally symmetric physical locations, inaccordance with an embodiment of the invention. As stated above, eachrow 21R comprises N pads 21, wherein N is an odd or even numberedinteger. For example, as shown in FIG. 12, each core circuit 10 has 4contact pads 21, such as a first pad P0, a second pad P1, a third padP2, and a fourth pad P3.

In one embodiment, each die 545 includes at least one row of M pads 21disposed on the peripheral area 545P of the die 545, wherein M is aninteger greater than 1. In one embodiment, each die 545 has a first side545A and a second side 545B that is opposite of the first side 545A. Letj denote the index of a pad 21 within a row disposed on the peripheralarea 545P of a die 545. As shown in FIG. 12, the pads 21 on theperipheral area 545P of each die 545 have horizontally symmetricalphysical locations. Specifically, each j^(th) pad within each row on theperipheral area 545P of each die 545 is arranged such that the distancefrom the first side 545A of the die 545 to said j^(th) pad is equal tothe distance from the second end 545B of the die 545 to the (M−j−1)^(th)pad of the row, wherein in j=0, . . . , M−1. For example, as shown inFIG. 12, each die 545 includes a first pad 21 and a second pad 21disposed on the peripheral area 545P of the die 545, wherein the firstpad 21 is positioned at a distance x₃ from the side 545A of the die 545,and the second pad 21 is positioned at a distance x₃ from the side 545Bof the die 545.

FIG. 13 illustrates core circuits 10 having an odd number of pads 21,wherein the pads 21 have vertically symmetrical physical locations, inaccordance with an embodiment of the invention. In one embodiment, eachcore circuit 10 has at least one column 21C of pads 21. Each column 21Ccomprises N pads 21, wherein N is an odd or even numbered integer. Forexample, as shown in FIG. 13, each core circuit 10 has 3 contact pads21, such as a first pad P0, a second pad P1, and a third pad P2.

Let i denote the index of a pad 21 within each column 21C. As shown inFIG. 13, the pads 21 on each core circuit 10 have vertically symmetricalphysical locations. Specifically, each i^(th) pad within a column 21C ofa core circuit 10 is arranged such that the distance from the first side10A of the core circuit 10 to said i^(th) pad is equal to the distancefrom the second end 10B of the core circuit 10 to the (N−i−1)^(th) padof the column 21C, wherein in i=0, . . . , N−1. For example, as shown inFIG. 13, the distance y₁ between pad P0 of core circuit Core0 and thefirst side 10A of core circuit Core0 is equal to the distance y₁ betweenpad P2 of core circuit Core0 and the second side 10B of core circuitCore0. Also shown in FIG. 13, the distance y₂ between pad P1 of corecircuit Core0 and the first side 10A of core circuit Core0 is equal tothe distance y₂ between pad P1 of core circuit Core0 and the second side10B of core circuit Core0.

In one embodiment, each die 545 has a peripheral area 545P with a widthy₀. The distance y₀ from an edge of the die 545 to an edge of the corecircuit Core0 is equal to the distance y₀ from an opposite edge of thedie 545 to an edge of the core circuit Core2.

Since the pads 21 on each core circuit 10 have vertically symmetricphysical locations, the pads 21 on a first die 545 vertically align withthe pads 21 on a second die 545 when the first and second dies 545 arebonded face-to-back, face-to-face, or back-to-back.

FIG. 14 illustrates core circuits 10 having an even number of pads 21,wherein the pads 21 have vertically symmetrical physical locations, inaccordance with an embodiment of the invention. As stated above, eachcolumn 21C comprises N pads 21, wherein N is an odd or even numberedinteger. For example, as shown in FIG. 14, each core circuit 10 has 4contact pads 21, such as a first pad P0, a second pad P1, a third padP2, and a fourth pad P3.

In one embodiment, each die 545 includes at least one column of M pads21 disposed on the peripheral area 545P of the die 545, wherein M is aninteger greater than 1. Let j denote the index of a pad 21 within acolumn disposed on the peripheral area 545P of a die 545. As shown inFIG. 14, the pads 21 on the peripheral area 545P of each die 545 havevertically symmetrical physical locations. Specifically, each j^(th) padwithin each column on the peripheral area 545P of each die 545 isarranged such that the distance from the first side 545A of the die 545to said j^(th) pad is equal to the distance from the second end 545B ofthe die 545 to the (M−j−1)^(th) pad of the row, wherein in j=0, . . . ,M−1. For example, as shown in FIG. 14, each die 545 includes a first pad21 and a second pad 21 disposed on the peripheral area 545P of the die545, wherein the first pad 21 is positioned at a distance y₃ from theside 545A of the die 545, and the second pad 21 is positioned at adistance y₃ from the side 545B of the die 545.

FIG. 15 illustrates straight-through buses 30, in accordance with anembodiment of the invention. Each pad 21 is configured to receive atleast one incoming bus signal 36 and send at least one outgoing bussignal 35. In one embodiment, each row 21R or column 21C of pads 21 hasat least one multiplexor structure (“multiplexor”) 40 that is configuredto enable mirror-reversing for the bus signals received by, or sent by,the pads 21. Specifically, each multiplexor 40 is configured forselecting between straight-through buses 30 or reversed buses 31 (FIG.17) for the bus signals based on a select bit Sel (e.g., from amirror-reversing module 175) that is set when the dies 545 of the arrayof processor core circuits are bonded face-to-face or back-to-back(i.e., set the select bit Sel to enable mirror-reversing).

For example, if Tiers 0 and 1 are bonded face-to-back as shown in FIG.15, each multiplexor 40 of each Tier 0, 1 selects straight-through buses30 for the bus signals. Therefore, outgoing bus signals 36 from Tier 1and Tier 0 are routed to Tier 0 and Tier 1, respectively, withoutmirror-reversing the bus signals. For example, an outgoing bus signalfrom pad P3 of the back contact 20B of Tier 1 is routed straight throughto pad P3 of the top contact 20A of Tier 0. As another example, anoutgoing bus signal from pad P0 of the top contact 20A of Tier 0 isrouted straight through to pad P0 of the back contact 20B of Tier 1.

FIG. 16 illustrates straight-through buses 30 and reversed buses 31, inaccordance with an embodiment of the invention. If Tiers 1 and 0 arebonded face-to-face as shown in FIG. 16, mirror-reversing is needed forsome bus signals. In one embodiment, each multiplexor 40 of Tier 1selects straight-through buses 30 and each multiplexor 40 of Tier 0selects reversed buses 31. The reversed buses 31 selected for Tier 0mirror-reverses the incoming bus signals 36. Specifically, each incomingbus signal 36 from a j^(th) pad within a row 21R/column 21C of M pads 21in Tier 1 is routed to the (M−j−1)^(th) pad of a row 21R/column 21C of Mpads 21 in Tier 0, wherein in j=0, . . . , M−1. For example, an incomingbus signal 36 from pad P3 of the top contact 20A of Tier 1 is routed topad P0 of the top contact 20A of Tier 0.

The reversed buses 31 selected for Tier 0 also mirror-reverses theoutgoing bus signals 35. Specifically, each outgoing bus signal 35 froma j^(th) pad within a row 21R/column 21C of M pads 21 in Tier 0 isrouted to the (M−j−1)^(th) pad of a row 21R/column 21C of M pads 21 inTier 1, wherein in j=0, . . . , M−1. For example, an outgoing bus signalfrom pad P0 of the top contact 20A of Tier 0 is routed to pad P3 of thetop contact 20B of Tier 1.

FIG. 17 illustrates core circuits 10 having pads 21 with verticallysymmetrical physical locations, wherein each pad 21 is disposed along acenter axis 10F of a core circuit 10, in accordance with an embodimentof the invention. In one embodiment, each core circuit 10 has Q pads 21,wherein Q is an integer greater than 1. Each pad 21 is physicallylocated along a center axis 10F of the core circuit 10. For example, asshown in FIG. 17, each core circuit 10 has 4 pads 21 disposed along thecenter axis 10F, such as a first pad P0, a second pad P1, a third padP2, and a fourth pad P3.

Let i denote the index of a pad 21 disposed along the center axis 10F ofa core circuit 10. As shown in FIG. 13, the pads 21 on each core circuit10 have vertically symmetrical physical locations. Specifically, eachi^(th) pad disposed along the center axis 10F of each core circuit 10 isarranged such that the distance from the first side 10A of the corecircuit 10 to said i^(th) pad is equal to the distance from the secondend 10B of the core circuit 10 to said i^(th) pad, wherein in i=0, . . ., Q−1. For example, as shown in FIG. 17, the distance y₁ between pad P3of core circuit Core0 and the first side 10A of core circuit Core0 isequal to the distance y₁ between pad P3 of core circuit Core0 and thesecond side 10B of core circuit Core0.

Since the pads 21 on each core circuit 10 have vertically symmetricalphysical locations, the pads 21 on a first die 545 vertically align withthe pads 21 on a second die 545 when the first and second dies 545 arebonded face-to-back, face-to-face, or back-to-back. Furthermore, nomirror-reversing of bus signals is needed when the pads 21 are disposedalong the center axis 10F of each core circuit 10, as described above.

FIG. 18 illustrates core circuits 10 having pads 21 with horizontallysymmetrical physical locations, wherein each pad 21 is disposed along acenter axis 10F of a core circuit 10, in accordance with an embodimentof the invention. As shown in FIG. 18, the pads 21 on each core circuit10 have horizontally symmetrical physical locations. Specifically, eachi^(th) pad disposed along the center axis 10F of each core circuit 10 isarranged such that the distance from the first side 10A of the corecircuit 10 to said i^(th) pad is equal to the distance from the secondend 10B of the core circuit 10 to said i^(th) pad, wherein in i=0, . . ., Q−1. For example, as shown in FIG. 18, the distance x₁ between pad P0of core circuit Core0 and the first side 10A of core circuit Core0 isequal to the distance x₁ between pad P0 of core circuit Core0 and thesecond side 10B of core circuit Core0.

Since the pads 21 on each core circuit 10 have horizontally symmetricalphysical locations, the pads 21 on a first die 545 horizontally alignswith the pads 21 on a second die 545 when the first and second dies 545are bonded face-to-back, face-to-face, or back-to-back. Furthermore, nomirror-reversing of bus signals is needed when the pads 21 are disposedalong the center axis 10F of each core circuit 10, as described above.

FIG. 19 is a high-level block diagram showing an information processingsystem 300 useful for implementing one embodiment of the invention. Thecomputer system includes one or more processors, such as processor 302.The processor 302 is connected to a communication infrastructure 304(e.g., a communications bus, cross-over bar, or network).

The computer system can include a display interface 306 that forwardsgraphics, text, and other data from the communication infrastructure 304(or from a frame buffer not shown) for display on a display unit 308.The computer system also includes a main memory 310, preferably randomaccess memory (RAM), and may also include a secondary memory 312. Thesecondary memory 312 may include, for example, a hard disk drive 314and/or a removable storage drive 316, representing, for example, afloppy disk drive, a magnetic tape drive, or an optical disk drive. Theremovable storage drive 316 reads from and/or writes to a removablestorage unit 318 in a manner well known to those having ordinary skillin the art. Removable storage unit 318 represents, for example, a floppydisk, a compact disc, a magnetic tape, or an optical disk, etc. which isread by and written to by removable storage drive 316. As will beappreciated, the removable storage unit 318 includes a computer readablemedium having stored therein computer software and/or data.

In alternative embodiments, the secondary memory 312 may include othersimilar means for allowing computer programs or other instructions to beloaded into the computer system. Such means may include, for example, aremovable storage unit 320 and an interface 322. Examples of such meansmay include a program package and package interface (such as that foundin video game devices), a removable memory chip (such as an EPROM, orPROM) and associated socket, and other removable storage units 320 andinterfaces 322, which allows software and data to be transferred fromthe removable storage unit 320 to the computer system.

The computer system may also include a communication interface 324.Communication interface 324 allows software and data to be transferredbetween the computer system and external devices. Examples ofcommunication interface 324 may include a modem, a network interface(such as an Ethernet card), a communication port, or a PCMCIA slot andcard, etc. Software and data transferred via communication interface 324are in the form of signals which may be, for example, electronic,electromagnetic, optical, or other signals capable of being received bycommunication interface 324. These signals are provided to communicationinterface 324 via a communication path (i.e., channel) 326. Thiscommunication path 326 carries signals and may be implemented using wireor cable, fiber optics, a phone line, a cellular phone link, an RF link,and/or other communication channels.

In this document, the terms “computer program medium,” “computer usablemedium,” and “computer readable medium” are used to generally refer tomedia such as main memory 310 and secondary memory 312, removablestorage drive 316, and a hard disk installed in hard disk drive 314.

Computer programs (also called computer control logic) are stored inmain memory 310 and/or secondary memory 312. Computer programs may alsobe received via communication interface 324. Such computer programs,when run, enable the computer system to perform the features of thepresent invention as discussed herein. In particular, the computerprograms, when run, enable the processor 302 to perform the features ofthe computer system. Accordingly, such computer programs representcontrollers of the computer system.

From the above description, it can be seen that the present inventionprovides a system, computer program product, non-transitorycomputer-useable storage medium, and method for implementing theembodiments of the invention. The non-transitory computer-useablestorage medium has a computer-readable program, wherein the program uponbeing processed on a computer causes the computer to implement the stepsof the present invention according to the embodiments described herein.References in the claims to an element in the singular is not intendedto mean “one and only” unless explicitly so stated, but rather “one ormore.” All structural and functional equivalents to the elements of theabove-described exemplary embodiment that are currently known or latercome to be known to those of ordinary skill in the art are intended tobe encompassed by the present claims. No claim element herein is to beconstrued under the provisions of 35 U.S.C. section 112, sixthparagraph, unless the element is expressly recited using the phrase“means for” or “step for.”

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. A processor array, comprising: a plurality ofsemiconductor dies, wherein each semiconductor die comprises at leastone processor core circuit; and a routing system for routing packetsbetween the semiconductor dies, wherein the routing system comprises atleast one interconnect circuit, each interconnect circuit correspondingto a semiconductor die of the semiconductor dies, the interconnectcircuit comprises a set of attachment pads interconnecting thesemiconductor die with a different semiconductor die of thesemiconductor dies, and the interconnect circuit is configured tocontrol routing of packets between the semiconductor die and thedifferent semiconductor die by: determining physical orientations of thesemiconductor die and the different semiconductor die based on one ormore physical properties associated with the set of attachment pads; inresponse to determining the physical orientations are same, routing thepackets between the semiconductor die and the different semiconductordie without mirror-reversing; and in response to determining thephysical orientations are different, routing the packets between thesemiconductor die and the different semiconductor die withmirror-reversing.
 2. The processor array of claim 1, wherein the one ormore physical properties associated with the set of attachment padscomprise at least one of physical locations, alignment and spacing ofthe set of attachment pads.
 3. The processor array of claim 1, whereinthe set of attachment pads are positioned substantially symmetrical onthe semiconductor die.
 4. The processor array of claim 1, wherein theset of attachment pads are positioned horizontally relative to oneanother on a processor core circuit of the semiconductor die.
 5. Theprocessor array of claim 1, wherein the set of attachment pads arepositioned vertically relative to one another on a processor corecircuit of the semiconductor die.
 6. The processor array of claim 1,wherein the set of attachment pads are positioned along a center axis ofa processor core circuit of the semiconductor die.
 7. The processorarray of claim 1, wherein: the packets are routed between thesemiconductor die and the different semiconductor die via a first set ofbuses without mirror-reversing the packets in response to determiningthe physical orientations are the same; and the packets are routedbetween the semiconductor die and the different semiconductor die via asecond set of buses that mirror-reverses the packets in response todetermining the physical orientations are different.
 8. A method,comprising: at a processor array comprising a plurality of semiconductordies: routing packets between the semiconductor dies via a routingsystem comprising at least one interconnect circuit, wherein eachinterconnect circuit corresponds to a semiconductor die of thesemiconductor dies, the interconnect circuit comprises a set ofattachment pads interconnecting the semiconductor die with a differentsemiconductor die of the semiconductor dies, and the interconnectcircuit is configured to control routing of packets between thesemiconductor die and the different semiconductor die by: determiningphysical orientations of the semiconductor die and the differentsemiconductor die based on one or more physical properties associatedwith the set of attachment pads; in response to determining the physicalorientations are same, routing the packets between the semiconductor dieand the different semiconductor die without mirror-reversing; and inresponse to determining the physical orientations are different, routingthe packets between the semiconductor die and the differentsemiconductor die with mirror-reversing; wherein each semiconductor diecomprises at least one processor core circuit.
 9. The method of claim 8,wherein the one or more physical properties associated with the set ofattachment pads comprise at least one of physical locations, alignmentand spacing of the set of attachment pads.
 10. The method of claim 8,wherein the set of attachment pads are positioned substantiallysymmetrical on the semiconductor die.
 11. The method of claim 8, whereinthe set of attachment pads are positioned horizontally relative to oneanother on a processor core circuit of the semiconductor die.
 12. Themethod of claim 8, wherein the set of attachment pads are positionedvertically relative to one another on a processor core circuit of thesemiconductor die.
 13. The method of claim 8, wherein the set ofattachment pads are positioned along a center axis of a processor corecircuit of the semiconductor die.
 14. The method of claim 8, wherein:the packets are routed between the semiconductor die and the differentsemiconductor die via a first set of buses without mirror-reversing thepackets in response to determining the physical orientations are thesame; and the packets are routed between the semiconductor die and thedifferent semiconductor die via a second set of buses thatmirror-reverses the packets in response to determining the physicalorientations are different.